Apache Design Launches RTL Power Model

By DE Editors

ANSYS subsidiary Apache Design has launched RTL Power Model (RPM) within Apache’s PowerArtist-XP software,  designed to optimize a wide range of power-sensitive applications, such as ultra-low-power electronics.

According to the company, RPM bridges the power gap from register-transfer-language (RTL) design to physical implementation. It accurately predicts integrated circuit (IC) power behavior at the RTL level with consideration for how the design is physically implemented. As a result, the technology helps to enable chip power delivery network (PDN) and IC package design decisions early in the design process, as well as to ensure chip power integrity sign-off for sub-28nm ICs.

RPMs core technologies include PowerArtist Calibrator and Estimator (PACE) for accurate power estimation at the RTL level prior to availability of physical layout as well as Fast Frame-Selector for critical power-aware cycle selection. PACE uses proprietary data-mining and pre-characterization techniques to create higher-quality power and capacitance models, as compared to traditional wire load models tuned for timing closure. Fast Frame-Selector technology performs power analysis on RTL simulation vectors and selects a set of the most power-critical cycles to use throughout the design flow, from early design planning to final chip sign-off.

For more information, visit Apache Design.

Sources: Press materials received from the company and additional information gleaned from the company’s website.