SynaptiCAD Releases VeriLogger Extreme, 1 in a Series

By DE Editors

The new compiled-code Verilog 2001 simulator from SynaptiCAD (Blacksburg, VA) reduces simulation debug time in both RTL and gate-level simulations with SDF timing information. VeriLogger Extreme supports design libraries and design flows for all major ASIC and FPGA vendors, including Actel, Altera, Atmel, LSI Logic, QuickLogic, and Xilinx.

VeriLogger Extreme comes bundled with SynaptiCAD’s graphical Verilog/VHDL integrated development environment, BugHunter Pro, for debugging with all major HDL simulators. BugHunter supports source-level debugging, a waveform compression engine for high-speed waveform dumping and viewing, and graphical test bench generation features for rapidly testing HDL models. BugHunter also supports importing and exporting simulation test vectors to Agilent and Tektronix pattern generators and logic analyzers.

VeriLogger Extreme uses 20 percent less memory than SynaptiCAD’s existing interpreted Verilog simulator, VeriLogger Pro. It is eight times faster than VeriLogger Pro for RTL-level simulation and 30 times faster for gate-level simulation.

VeriLogger Extreme is available on Linux, Solaris, and Windows. For more information, visit syncad.com.

Sources: Press materials received from the company and additional information gleaned from the company’s website.